1. Field of the Invention
The present invention relates generally to semiconductor memory devices and a manufacturing method thereof, and more particularly, to semiconductor memory devices formed on semiconductor substrates having at least one memory cell array region at which a plurality of memory cells each comprising a transistor and a capacitor are formed and a peripheral circuit region at which a plurality of transistors for peripheral circuits are formed, and a method of manufacturing such semiconductor memory devices.
2. Description of the Background Art
In recent years, a remarkable spread of information apparatus such as computers has been increasing a demand for semiconductor memory devices. In particular, semiconductor memory devices having a large storage capacity and operable at a high speed are in great demand, which demand is followed by technological development to improve integration density, response and reliability of semiconductor memory devices.
Out of semiconductor memory devices, a DRAM (Dynamic Random Access Memory) is well known as a memory which enables random input and output of storage information. A DRAM generally comprises a memory cell array portion serving as a storage region wherein a lot of storage information is stored and a peripheral circuit portion for inputting/outputting external signals. FIG. 4 is a block diagram showing an arrangement of a common DRAM. With reference to FIG. 4, a DRAM 50 comprises a memory cell array 51 for storing data signals of storage information, a row and column address buffer 52 for receiving external address signals for selecting memory cells constituting an unit storage circuit, a row decoder 53 and a column decoder 54 for designating a memory cell by decoding the address signals, a sense refresh amplifier 55 for amplifying the signal stored in the designated memory cell and reading the amplified signal, a data-in buffer 56 and data-out buffer 57 for inputting and outputting data, respectively, and a clock generator 58 for generating clock signals.
Memory cell array 51 occupying a large area of a semiconductor chip includes a plurality of memory cells for storing unit storage information arranged in a matrix. In general, as a memory cell, a one-transistor one-capacitor type memory cell is known which comprises one MOS transistor and one capacitor connected thereto. A memory cell of such simple arrangement enables an increase in integration of a memory cell array with ease, which fact leads to a wide use of such memory cell in a DRAM having a large capacity.
Memory cells for use in a DRAM fall into several types depending on capacitor arrangement. A stacked type capacitor, a main part of which extends above a gate electrode and a field isolating film, enables an increase in opposing areas of electrodes of the capacitor, thereby increasing a capacitance of the capacitor. The stacked type capacitor having such characteristic ensures a capacitor capacitance even when elements are made small in scale as an integration density of a semiconductor device is increased. As a result, an increase in integration density of a semiconductor memory device leads to a frequent use of a stacked type capacitor. Integration density of a semiconductor memory device has been further increased, which is followed by an improvement in a stacked type capacitor.
FIG. 5 is a diagram showing an arrangement of the respective components of the DRAM shown in FIG. 4. With reference to FIG. 5, column decoder 54 and sense refresh amplifier 55 are laterally arranged adjacent to memory cell array 51. Raw decoder 53 is vertically arranged adjacent to memory cell array 51. A plurality of memory cell arrays 51 are arranged each having vertically disposed row decoder 53 and laterally disposed column decoder 54 and sense refresh amplifier 55. Memory cell array 51 comprises a plurality of memory cells (not shown) arranged corresponding to a storage capacity. Row and column address buffer 52 is vertically arranged at the center of DRAM 50. Input portions corresponding to address inputs A.sub.0 -A.sub.9 are arranged surrounding the plurality of memory cell arrays 51. A data out buffer 57 and Vss connected to the outside of the DRAM are arranged at the opposite sides of the DRAM 50 in the vertical direction.
FIG. 6 is a plan view showing a wiring pattern taken along X--X of the DRAM shown in FIG. 5 and FIG. 7 is a diagram showing the sectional arrangement of the DRAM shown in FIG. 6. With reference to FIG. 6, a peripheral circuit portion (Vcc power supply portion, column decoder) and a memory cell portion in a conventional DRAM differ in density of a formed wiring pattern. That is, while the wiring pattern is formed to have a high density in the memory cell portion, the pattern is formed to have a low density in the peripheral circuit portion. This is because integration of the memory cell portion is further increased to meet the requirement on an increase in storage capacity, while the peripheral circuit portion needs not to be so highly integrated as compared with the memory cell portion. With reference to FIGS. 6 and 7, a plurality of gate electrodes 6a of transfer gate transistors 20 each constituting one memory cell are arranged spaced apart from each other at predetermined intervals in the memory cell portion. Gate electrodes 106b of transfer gate transistors 21 are arranged in a column decoder region in the peripheral circuit portion at spacing larger than that of gate electrodes 6a in the memory cell portion. In a Vcc power supply portion in the peripheral circuit portion, wiring layers 106c are arranged at spacing larger than that of gate electrodes 6a in the memory cell portion.
An arrangement of a conventional DRAM will be described with reference to FIG. 7. The DRAM comprises a memory cell portion and a peripheral circuit portion. The memory cell portion includes a memory cell comprising one transfer gate transistor 20 and one capacitor 30, and a bit line 12 for transferring electric charges stored in the capacitor 30 of the memory cell.
Transfer gate transistor 20 constituting the memory cell comprises the above-described gate electrode 6a formed on an oxide film 5 formed on a semiconductor substrate 1, and impurity regions 3 and 4 formed at semiconductor substrate 1 at the opposite sides of gate electrode 6a.
Capacitor 30 comprises a storage node 8 electrically connected to one impurity region 3 of transfer gate transistor 20 and a cell plate 10 formed on storage node 8 with a dielectric film 9 provided therebetween. Bit line 12 is electrically connected to the other impurity region 4 of transfer gate transistor 20. A field insulation film 2 for isolating adjacent elements is formed at semiconductor substrate 1. Gate electrodes 6a are also formed spaced apart from each other at a predetermined distance on field insulation film 2 with oxide film 5 provided therebetween. An interlayer insulation film 11 is formed between cell plate 10 of capacitor 30 and bit line 12. An interlayer insulation film 7 is formed between storage node 8 and gate electrode 6a. An interlayer insulation film 13 is formed on bit line 12. Formed on interlayer insulation film 13 are aluminum wiring layers 14 at specific spacing to correspond to gate electrodes 6a.
The column decoder in the peripheral circuit portion includes two transfer gate transistors 21. Transfer gate transistor 21 comprises gate electrode 106b formed on oxide film 5 formed on semiconductor substrate 1 and impurity regions 3, 4 formed at semiconductor substrate 1 at the opposite sides of gate electrode 106b. Formed on transfer gate transistor 21 is interlayer insulation film 11 on which aluminum wirings 14 are formed to correspond to gate electrodes 106b.
The Vcc power supply portion in the peripheral circuit portion comprises wiring layers 106c connected to the power supply Vcc. Wiring layers 106c are arranged on oxide film 5 formed on semiconductor substrate 1 at specific spacing. Formed on wiring layers 106c is interlayer insulation film 11 on which aluminum wirings 14 are formed to correspond to wiring layers 106c.
For writing to a conventional DRAM having such arrangement, a column decoder in the peripheral circuit portion or the like first designates a memory cell. Then, signal charges are transmitted through bit line 12 to the designated memory cell. The signal charges transmitted through bit line 12 are transmitted to storage node 8 of capacitor 30 by applying predetermined charges to gate electrode 6a. The signal charges transmitted to storage node 8 are stored in capacitor 30. In a reading operation, signal charges are transmitted onto bit line 12 by applying a predetermined voltage to gate electrode 6a. The signal charges transmitted onto bit line 12 are externally read out through the column decoder (see FIG. 4).
As described above, in the conventional DRAM having such arrangement and operation, the density of the wiring pattern formed in the memory cell portion is higher than that of the wiring pattern formed in the peripheral circuit portion. FIGS. 8A to 8D are sectional views explaining a process of forming a wiring pattern of the DRAM shown in FIG. 6. The process of forming a wiring pattern will be described with reference to FIGS. 8A to 8D. With reference to FIG. 8A, a field insulation film 2 is formed at a semiconductor substrate 1. An oxide film 5 is formed on semiconductor substrate 1 and field insulation film 2. Formed on oxide film 5 is a polysilicon layer 6 on which a resist 140 is applied, which is exposed by using a photomask 141 previously prepared corresponding to the wiring pattern. Thereafter, resist 140 at a region wherein no wiring pattern is formed is removed by a development processing. With reference to FIG. 8B, etching is carried out by using the remaining resist 140 as a mask. As a result, the wiring pattern as shown in FIG. 8C is formed. As shown in FIG. 8D, a removal of resist 140 obtains a predetermined wiring pattern. After such processes the DRAM as shown in FIG. 7 is completed through an ordinary process.
As described above, in a conventional DRAM, a density of a wiring pattern formed in a memory cell portion is higher than that of a wiring pattern formed in a peripheral circuit portion. In other words, the spacing between gate electrodes 6a formed in the memory cell portion is narrower than that between gate electrodes 106b formed in the peripheral circuit portion. In such a case as spacing between gate electrodes varies, the following problems arise on a manufacturing process.
More specifically, the peripheral circuit portion with large wiring spacing requires more development amount at the time of exposing and developing resist 140 as compared with the development amount in the memory cell portion. A large development amount makes in the final resist width larger than that with a less development amount. This is partly because a large development amount per unit area of the resist reduces a development density. For the similar reason, the etching amount at the time of formation of the wiring pattern is increased in the peripheral circuit portion having wide spacing between wirings and the width of the final wiring pattern is increased accordingly. These phenomenons are referred to as loading effect, which is disclosed in "SOLID-STATE SCIENCE AND TECHNOLOGY August 1977-The Loading Effect in Plasma Etching", for example.
In other words, in a conventional DRAM, a development amount of a resist and an etching amount of a polysilicon layer per unit area are larger in a peripheral circuit portion than in a memory cell portion at the time of forming wiring patterns, thereby making the final wiring patterns wider than that designed in advance. As described in the foregoing, a transistor characteristic is deteriorated when a wiring pattern using a planned width can not be obtained, which pattern uses, for example, gate electrode 106b constituting transfer gate transistor 21 of the peripheral circuit portion shown in FIG. 7. The deteriorated transistor characteristic of transfer gate transistor 21 in the peripheral circuit portion leads to deterioration in a memory characteristic. Reading and writing from/to the DRAM is carried out by using transfer gate transistor 21 of the peripheral circuit as described above. The deteriorated characteristic of transfer gate transistor 21 therefore prevents reliable reading and writing operation from/to the DRAM. As a result, the memory characteristic of the DRAM is deteriorated.